1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a content addressable memory (CAM) for determining whether search data is stored in accordance with the search data. More particularly, the present invention relates to a ternary content addressable memory (TCAM) capable of performing high-speed operation and stably storing ternary data.
2. Description of the Background Art
A content addressable memory (CAM) has functions of writing and reading data and, in addition, capable of addressing stored data in accordance with search data. Specifically, a CAM can detect whether stored data (word) which matches external data (search data), exists. When data matching the search data is stored, a match line is driven and it can be detected that data matching the search data is stored. Therefore, it is unnecessary to compare stored data with search data one by one, so that data search can be performed at high speed.
Such a CAM is used for, for example, address comparison at the time of determination of cache hit/miss for determining whether necessary data is stored or not in accessing a cache in a data processing system.
In a conventional CAM, a memory cell has, as storage states, two states of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d and stores binary data. In the case of the CAM for storing binary data, non-ambiguous and meaningful data is stored for each word. In a search operation, when bits of stored data (word) completely match bits of search data, a match line is set to a state indicative of match.
A TCAM (Ternary CAM) for storing ternary data in place of a CAM cell for storing binary data is disclosed in U.S. Pat. No. 6,320,777 B1.
In the TCAM, as storage states, in addition to the two states of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, a xe2x80x9cdon""t care (X)xe2x80x9d state is stored in a memory cell. In the case of constructing each storage word by a combination of ternary data bits, it is particularly effective in the case of performing a process on an IP (Internet Protocol) packet in a network system. For example, it is now assumed that a destination address of a packet is expressed by four bits, for simplicity. When the destination address of a packet is xe2x80x9c1***xe2x80x9d (where the head bit is xe2x80x9c1xe2x80x9d and each of the remaining address bits may be any value), a predetermined process is assumed to be performed on the packet. In addition, to retrieve the destination address when the packet arrives at the system and determine whether the destination address matches the address xe2x80x9c1***xe2x80x9d or not, the content addressable memory CAM or the ternary CAM is assumed to be used.
In this case, the data xe2x80x9c1***xe2x80x9d has to be stored in the CAM or TCAM before the packet arrives. When a normal CAM for storing binary data is used, eight states of xe2x80x9c1000xe2x80x9d, xe2x80x9c1001xe2x80x9d, xe2x80x9c1010xe2x80x9d, xe2x80x9c1011xe2x80x9d, xe2x80x9c1100xe2x80x9d, xe2x80x9c1101xe2x80x9d, xe2x80x9c1110xe2x80x9d, and xe2x80x9c1111xe2x80x9d have to be stored. Therefore, for retrieval of the destination address of the packet, eight words are consumed.
By contrast, since a state xe2x80x9cXxe2x80x9d can be stored in the TCAM, TCAM is only required to store one word of xe2x80x9c1XXXxe2x80x9d. When the number of bits of the destination address further increases, the difference in the number of words to be used further increases. Therefore, in the case of using the TCAM, various data can be stored with a reduced number of words. In practice, an IP packet includes, in addition to the destination address, various information such as an IP address of a transmission source, information indicative of communication quality, and version number of an IP protocol. It is therefore understood that the TCAM is very useful in the case of performing a search process on the information.
As described above, the TCAM is a content addressable memory capable of storing ternary information and is useful as an LSI used for packet search information in an information network system.
In the prior art document as described previously, a DRAM (Dynamic Random Access Memory) cells of two bits are used to store 1-bit data, thereby achieving storage of ternary data. Specifically, data of xe2x80x9cHLxe2x80x9d, xe2x80x9cLHxe2x80x9d and xe2x80x9cLLxe2x80x9d is stored in two separate storage nodes of the DRAM cells, and a comparing circuit detects whether the data matches search data supplied via a search data line or not.
As described above, in the prior art document, a DRAM cell is used as a memory element. As a capacitive element for storing data in the DRAM cell, a three-dimensional capacitor of a stacked structure is used. If such stacked capacitor is used in the DRAM cell, it is excepted that the area of a TCAM cell can be reduced and the chip area is accordingly reduced. It is also expected that a capacitor, which occupies a small area but has a large capacitance value, can be implemented and a soft error immunity can be improved.
In the case of using such a stacked capacitor for a TCAM, however, in order to make the operation stable, it is necessary to form a capacitor of as large a capacitance value as possible. Consequently, the structure of a capacitor portion is complicated and a memory cell structure becomes a complicated three-dimensional structure. Accordingly, the number of processes and the number of masks increase, and complicated patterning has to be made, so that it becomes difficult to decrease the chip cost. Consequently, even when the stacked capacitor of the three-dimensional structure is used to reduce the TCAM cell area to reduce the chip area accordingly, it is difficult to dramatically decrease the manufacturing cost.
As for electric characteristics, usually, a DRAM cell capacitor can have a large capacitance value. On the other hand, it takes long time to charge the capacitor and it causes such a problem that write cycle time is increased. In the TCAM, when it is necessary to write data to an array, the data has to be written while interrupting a normal search operation. Therefore, in the case in which the write time is long, the interruption time against the search operation is correspondingly increased, and it causes such a problem that the search process efficiency deteriorates.
In the case of using the capacitor of a DRAM cell for storing data, in order to prevent stored data from being lost by leakage of charges, a refresh operation for restoring data has to be performed periodically. In performing the refresh operation, memory cell information is internally read, amplified and rewritten. Therefore, the refresh operation has to be performed also while interrupting the search operation. Since the interruption by the refresh operation to the search operation occurs in a major time portion, the search process efficiency deteriorates.
In the configuration of the TCAM cell shown in the prior art document 1, an open bit line structure for amplifying potentials of bit lines that are provided on the right and left sides of a sense amplifier is employed inevitably for the following reason. A sense amplifier is used to read and refresh data of the TCAM cell. A bit line is connected to a transistor in the DRAM cell in the TCAM cell and transmits write/read data.
The potentials of the storage nodes of the two capacitors in the TCAM cell are xe2x80x9cH, Lxe2x80x9d, xe2x80x9cL, Hxe2x80x9d or xe2x80x9cL, Lxe2x80x9d in accordance with a storage state. Therefore, complementary voltages are not always stored in the two storage nodes. When data stored in the two capacitors of TCAM cell are read to first and second bit lines, voltages of the first and second bit lines cannot be differentially amplified by a sense amplifier. Thus, a normal folded bit line structure used in a DRAM cannot be used.
In the case of the folded bit line configuration, complementary data are always transmitted to a pair of bit lines, and a sense amplifier amplifies the difference of the potentials on the bit line pair. The bit line pair is disposed in parallel on one side of the sense amplifier. Even if noise occurs, common phase noises also occur on the bit line pair. Different from the open bit line configuration, the folded bit line configuration has an advantage that influences of noise are cancelled out and a very small potential difference can be stably amplified. In the case of the TCAM cell in the prior art document, bit lines are disposed in the open bit line configuration, so that the TCAM cell is vulnerable to noise and a problem arises that it is difficult to perform a sensing operation stably.
In place of the configuration of using the 2-bit DRAM cells as the TCAM cell, it is also possible to use an SRAM (Static Random Access Memory) cell constructed by an inverter latch for a 2-bit data storage element. In the case of using an SRAM cell, the refresh operation is unnecessary, and the search process efficiency can be improved as compared with the DRAM cell. In the case in which an MIS transistor (insulated gate field effect transistor) is used for an SRAM cell, the capacitance of a storage node of the SRAM cell is a gate capacitance of the MIS transistor. As the capacitance value is smaller as compared with the DRAM cell capacitor, the storage node can be charged at high speed, and data can be written at high speed.
However, since a parasitic capacitance of the storage node is small, due to an impact ionization phenomenon that occurs in a substrate region when an alpha ray is irradiated, a soft error that charges of the storage node disappear through recombination and the stored data changes tends to occur. A problem arises that immunity against a soft error caused by alpha ray is very low.
Since the SRAM cell is constructed by an inverter latch, in the case of using the SRAM cells of two bits in order to store data of one bit, for a full CMOS (complementary MIS) cell, eight MIS transistors in total are required. The area occupied by the cell increases and it causes a problem that the chip area cannot be reduced
An object of the present invention is to provide a semiconductor memory device having a TCAM cell capable of storing data stably with a reduced area.
Another object of the present invention is to provide a semiconductor memory device having a TCAM cell capable of writing data at high speed.
Still another object of the present invention is to provide a large-storage-capacity, high-speed, and low-cost semiconductor memory device.
In a semiconductor memory device according to the present invention, a data storage section of a TCAM cell for storing 1-bit data is constructed by first and second twin cells each including two DRAM cells.
The TCAM cell according to the present invention further includes a comparing circuit for comparing data stored in a storage node in the first twin cell with data transmitted via a first search data line in a search data line pair, comparing data stored in a storage node in the second twin cell with search data transmitted via a second search data line in the search data line pair, and selectively driving a match line in accordance with result of the comparison. To the search data line pair, complementary data are transferred.
The TCAM cell is constructed by two DRAM twin cells in which complementary data are normally stored. The difference between the complementary data in the twin cell can be amplified by a sense amplifier. A sensing operation can be performed in the folded bit line configuration.
Since complementary data are stored in the twin cell and a voltage difference always exists between the storage nodes, a voltage difference can be caused between the bit line pair at the time of internally reading data. Consequently, a refresh interval can be increased, deterioration in search efficiency is suppressed, and current consumption required for refresh is reduced.
Since the DRAM cells are used as components of the twin cells, as compared with the configuration of using an SRAM cell, the occupying area can be reduced, and a TCAM cell of a reduced occupying area can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.